1. Field of the Invention
The present invention relates to a floating type D/A conversion apparatus that performs level conversion on input digital data with different conversion factors, converts the digital data into respective analog signals, and then adds the analog signals after re-converting them into the original level, to thereby provide a wide dynamic range.
2. Prior Art
With an improvement in the conversion accuracy of A/D converters due to development of .DELTA..SIGMA. modulators of higher order in recent years, D/A converters have been desired to provide even higher resolution and wider dynamic range. To this end, floating type D/A conversion apparatuses have been developed which use D/A converters (hereinafter referred to as "DAC") capable of converting a limited number of bits, for obtaining higher resolution and wider dynamic range beyond the limited number of conversion bits. In this type of apparatus, when DAC (D/A converter) of N bits (for example, 20 bits) is used for converting digital data of M bits (for example, 24 bits, M&gt;N) where the significant bits of the data are P bits (M.gtoreq.P&gt;N), the DAC converts the digital data as it is into a corresponding analog signal, while truncating or discarding less significant M-N bits (for example, 4 bits). When the output level of the digital data is lowered, and the significant word length becomes equal to P' bits (P.ltoreq.N), the conversion apparatus multiplies the digital data by 2.sup.M-N, namely, shifts the original data toward the MSB (most significant bit) by M-N bits, while filling the less significant M-N bits with zero, and then converts the obtained digital data into an analog signal. Whether the input digital data should be converted without being changed, or multiplied by 2.sup.M-N before D/A conversion, is determined depending upon whether overflow occurs (the digital input level exceeds a threshold value) after shifting the input digital data by M-N bits.
With the above-described conversion, when the significant bits of the data is equal to P bits, almost no adverse influence arises from the truncation of the less significant bits since the converted word length is sufficiently large. Even if any problem arises, dithering, or other operation, may be performed as needed to eliminate the problem. Where the significant bit length is equal to P', on the other hand, the data is multiplied by 2.sup.M-N, and the less significant M-N bits are truncated or discarded during the D/A conversion, so that the DAC can effectively convert digital data of the less significant M-N bits that would be otherwise truncated if the data is not multiplied by 2.sup.M-N, into a corresponding analog signal, thus assuring higher resolution and wider dynamic range. In the latter case, however, the analog signal generated by the DAC, which has also been multiplied by 2.sup.M-N, need be multiplied by 1/2.sup.M-N, so that the level of the analog output matches that of the original digital data.
In one known example of floating type D/A conversion apparatus using a single DAC, the gain of an analog amplifier that amplifies the output of the DAC is changed according to a level conversion factor with which input digital data was converted. In another example as disclosed in Japanese Patent Publication (Kokoku) No. 7-93579, a plurality of DACs are used for converting a plurality of digital data that have been converted to different levels with different conversion factors, into respective analog signals, and a selected one of the outputs of the DAC is generated, for which the level conversion was performed with the most appropriate conversion factor.
In the former type of the known floating type D/A conversion apparatus, however, the gain of the analog amplifier must be instantly changed upon a change in the level of the digital data, and, if the output of the amplifier does not immediately follow the change in the level of the digital data, or the DC offset of the amplifier varies, uncomfortable noise may arise which cannot be aurally ignored. In the latter type of apparatus that selects one of the analog signals generated by the DAC, there is also a problem of transient noise upon switching of the analog signals. These problems may become extremely serious where the resolution of digital data to be processed reaches a low-noise region in which the SN ratio ranges from 120 to 140 decibels, which could be resolved only by a known analog circuit arrangement.